A Low Power Comparator Design for 6-Bit Flash ADC in 90-Nm CMOS
نویسنده
چکیده
The main focus of this paper is to design a “Low power Flash ADC” for ultra-wide band applications using CMOS 90nm technology. Flash ADC consists of a reference generator, array of comparators, 1-out-of N code generator, Fat tree encoder and output D latches. The demanding issues in the design of a low power flash ADC is the design of low power latched comparator. The proposed comparator in this paper is designed using 90nm technology at 0.8V DC voltage source using H SPICE tool. The Simulation results of a 6-bit flash ADC is shown for a sampling frequency up to 1.2GHz showing an average power dissipation of 7.67mW.
منابع مشابه
Low Power Flash ADC
In this paper, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1GHz, is implemented in a 1.2 V analog supply voltage. HSpice simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes less power i n a commercial 90n...
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